## Verilog

`Type`

`Name`

(`Output`

, `Onput`

)

## Gate

**NOT**: `'`

`not n1(f, x);`

**AND**: `*`

```
// multi input allowed
and d1(f, x, y);
```

zero times everything is also zero, which obey the characteristic of or operation

**OR**: `+`

```
// multi input allowed
or d2(f, x, y);
```

single one value cause the output become one

**XOR: ⊕**

True only when input is **not same**

```
// multi input allowed
xor d3(f, x, y);
```

also have the property of being the toggle, i.e.

0 and 1 there iscontrol, and x isdata

$$ x \oplus 0 = x $$

$$ x \oplus 1 = x' $$

## Expression

$$ f(x,y)=(x+y)y' $$

```
wire x, y, o1, o2, f;
or o1(o1, x, y);
not n1(o2, y);
and a1(f, o1, o2);
```

## Test of Verilog

```
module sc_test;
reg a, b; // input
wire s, c // output
sc_block sc1(s, c, a, b) // build circuit under test
initial begin
$dumpfile("sc.vcd"); // output file config
$dumpvars(0, sc_test) // test what module and how to test?
a = 0; b = 0; #10; // test signal for 10 sec
a = 0; b = 1; #10;
a = 1; b = 0; #10;
$finish; // end simulation
end
initial
$monitor("At time %2t, a = %d b = %d s = %d c = %d", $time, a, b, s, c); // format the string and record
endmodule // end test
```

## Operation

### Bitwise Operation

do operation to every bit

```
unsigned char a = 0xac; // bit value
unsigned char b = ~a; // apply not gate to every bit
```

### Logical Operation

- have higher priority than bitwise operation

**True**: if bits have `1`

**False**: all bits are `0`

## Base transfer

**Base 2 to 10**: each position times weight, i.e. $2^x$

**Base 10 to 2**: divided by 2 till answer is 0, list remainder of each steps and write them down inversely.

**Base 2 to 16**: divided them into groups (four item per groups), then, convert each block into base 16

## Binary addition

**Modular Addition**: Not like normal addition or subtraction, binary addition/subtraction cannot carry last character.

A +B in N-bit representation is equal to:

$$ (A + B)mod 2^N $$

### Overflow

If expectation not equal to reality, overflow happens

$$ A + B \not = (A+ B )mod 2^n $$

## 2's Complement Representation

Use base 2 to represent the sign

Compare with the normal representation, it can do calculation right even when discard the last character

### Change sign

- origin: 0 0 1 1
- flip bit: 1 1 0 0
- add one: 1 1 0 1

### Overflow

for example, 4-bits 2's Comp representation range from -8 to 7

- We can simply check if overflow by checking the result sign

### Bit shift

define in programming by declare `unsign`

**left shift**: append to the left, and discard the right most bit, **sign/unsigned behave identically**

**right shift**:

**unsigned**: append all zero on the right**signed**: append bit according to the foremost bit (negative/positive)

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